1. Field of the Invention
The present invention relates to floating point units and, more particularly, but not by way of limitation, to a method and apparatus for rounding the result of an arithmetic operation.
2. Description of the Related Art
In order to produce answers that conform with the IEEE/ANSI 754-1985 standard for Floating Point Arithmetic, floating point units must output a mantissa that includes the number of bits required under the standard. Floating point units typically produce more bits than necessary to form the mantissa bits as specified in the IEEE 754-1985 standard and then round according to the additional bits. Traditionally, for iterative operations such as division or square root, the floating point unit produces twice as many bits as required for an IEEE standard mantissa. However, producing twice as many bits significantly decreases the operating speed of the floating point unit because that requires an increased number of clock cycles.
In an attempt to reduce the number of clock cycles required to perform iterative operations, floating point units include a circuit that examines a number of additional bits to determine if the mantissa forms the correct answer. If it is determined that the mantissa does not form the correct answer, incrementing of the mantissa might be necessary. When the mantissa does not form the correct answer, a series of operations are launched through the floating point unit that determine if the mantissa bits must be incremented. Unfortunately, these operations are not independent in that later operations require answers from prior operations before they can execute. Consequently, when the additional operations are necessary, the number of clock cycles required to determine the final mantissa can increase to an unacceptable level.
Accordingly, circuitry that decreases the number of clock cycles required to round results of iterative arithmetic operations will improve the performance of floating point units.